External Memory Interfaces Intel® Agilex™ FPGA IP Design Example User Guide

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ID 683162
Date 6/21/2021
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2.10.1. Enabling the Traffic Generator in a Design Example

You can enable the configurable traffic generator from the Diagnostics tab in the EMIF parameter editor.

To enable the configurable traffic generator, turn on Use configurable Avalon traffic generator 2.0 on the Diagnostics tab.

Figure 6. 
  • You may choose to disable the default traffic pattern stage or the user-configured traffic stage, but you must have at least one stage enabled. For information on these stages, refer to Default Traffic Pattern and User-configured Traffic Pattern in the External Memory Interfaces Intel® Agilex™ FPGA IP User Guide.
  • The TG2 test duration parameter applies only to the default traffic pattern. You may choose a test duration of short, medium, or infinite.
  • You may choose either of two values for the TG2 Configuration Interface Mode parameter:
    • JTAG: Allows use of a GUI in the system console. For more information, refer to Traffic Generator Configuration Interface in the External Memory Interfaces Intel® Agilex™ FPGA IP User Guide.
    • Export: Allows use of custom RTL logic to control the traffic pattern.

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