External Memory Interfaces Intel® Agilex™ FPGA IP Design Example User Guide

Download PDF
ID 683162
Date 6/21/2021
Public

A newer version of this document is available. Customers should click here to go to the newest version.

Document Table of Contents
Document Table of Contents x
1. About the External Memory Interfaces Intel® Agilex™ FPGA IP 2. Design Example Quick Start Guide for External Memory Interfaces Intel® Agilex™ FPGA IP 3. Design Example Description for External Memory Interfaces Intel® Agilex™ FPGA IP 4. External Memory Interfaces Intel® Agilex™ FPGA IP Design Example User Guide Archives 5. Document Revision History for External Memory Interfaces Intel® Agilex™ FPGA IP Design Example User Guide
1. About the External Memory Interfaces Intel® Agilex™ FPGA IP x
1.1. Release Information
2. Design Example Quick Start Guide for External Memory Interfaces Intel® Agilex™ FPGA IP x
2.1. Creating an EMIF Project 2.2. Generating and Configuring the EMIF IP 2.3. Generating the Synthesizable EMIF Design Example 2.4. Generating the EMIF Design Example for Simulation 2.5. Simulation Versus Hardware Implementation 2.6. Simulating External Memory Interface IP With ModelSim 2.7. Pin Placement for Intel® Agilex™ EMIF IP 2.8. Compiling and Programming the Intel® Agilex™ EMIF Design Example 2.9. Generating a Design Example with the Calibration Debug Option 2.10. Generating a Design Example with the TG Configuration Option 2.11. Using the Design Example with the EMIF Debug Toolkit
2.2. Generating and Configuring the EMIF IP x
2.2.1. Intel® Agilex™ EMIF Parameter Editor Guidelines
2.10. Generating a Design Example with the TG Configuration Option x
2.10.1. Enabling the Traffic Generator in a Design Example
3. Design Example Description for External Memory Interfaces Intel® Agilex™ FPGA IP x
3.1. Synthesis Design Example 3.2. Simulation Design Example 3.3. Example Designs Interface Tab
1. About the External Memory Interfaces Intel® Agilex™ FPGA IP
2. Design Example Quick Start Guide for External Memory Interfaces Intel® Agilex™ FPGA IP
3. Design Example Description for External Memory Interfaces Intel® Agilex™ FPGA IP
4. External Memory Interfaces Intel® Agilex™ FPGA IP Design Example User Guide Archives
5. Document Revision History for External Memory Interfaces Intel® Agilex™ FPGA IP Design Example User Guide

5. Document Revision History for External Memory Interfaces Intel® Agilex™ FPGA IP Design Example User Guide

Document Version Intel® Quartus® Prime Version IP Version Changes
2021.06.21 21.2 2.4.2 In the Design Example Quick Start chapter:
  • Added a note to the Compiling and Programming the Intel® Agilex™ EMIF Design Example topic.
  • Modified the title of the Generating a Design Example with the Calibration Debug Option topic.
  • Added the Generating a Design Example with the TG Configuration Option and Enabling the Traffic Generator in a Design Example topics.
  • Modified steps 2, 3, and 4, updated several figures, and added a note, in the Using the Design Example with the EMIF Debug Toolkit topic.
2021.03.29 21.1 2.4.0 In the Design Example Quick Start chapter:
  • Added a note to the Generating the Synthesizable EMIF Design Example and Generating the EMIF Design Example for Simulation topics.
  • Updated the File Structure diagram in the Generating the EMIF Design Example for Simulation topic.
2020.12.14 20.4 2.3.0 In the Design Example Quick Start chapter, made the following changes:
  • Updated the Generating the Synthesizable EMIF Design Example topic to include multi-EMIF designs.
  • Updated the figure for step 3, in the Generating the EMIF Design Example for Simulation topic.
2020.10.05 20.3 2.3.0 In the Design Example Quick Start Guide chapter, made the following changes:
  • In Creating an EMIF Project, updated the image in step 6.
  • In Generating the Synthesizable EMIF Design Example, updated the figure in step 3.
  • In Generating the EMIF Design Example for Simulation, updated the figure in step 3.
  • In Simulation Versus Hardware Implementation, corrected a minor typo in the second table.
  • In Using the Design Example with the EMIF Debug Toolkit, modified step 6, added steps 7 and 8.
2020.04.13 20.1 2.1.0
  • In the About chapter, modified the table in the Release Information topic.
  • In the Design Example Quick Start Guide chapter:
    • Modified step 7 and the associated image, in the Generating the Synthesizable EMIF Design Example topic.
    • Modified the Generating the Design Example with the Debug Option topic.
    • Modified the Using the Design Example with the EMIF Debug Toolkit topic.
2019.12.16 19.4 2.0.0
  • In the Design Example Quick Start chapter:
    • Updated the illustration in step 6 of the Creating an EMIF Project topic.
    • Updated the illustration in step 4 of the Generating the Synthesizable EMIF Design Example topic.
    • Updated the illustration in step 4 of the Generating the EMIF Design Example for Simulation topic.
    • Modified step 5 in the Generating the EMIF Design Example for Simulation topic.
    • Modified the General Pin Guidelines and Adjacent Banks sections of the Pin Placement for Intel Agilex EMIF IP topic.
2019.10.18 19.3  
  • In the Creating an EMIF Project topic, updated the image with point 6.
  • In the Generating and Configuring the EMIF IP topic, updated the figure with step 1.
  • In the table in the Intel Agilex EMIF Parameter Editor Guidelines topic, changed the description for the Board tab.
  • In the Generating the Synthesizable EMIF Design Example and Generating the EMIF Design Example for Simulation topics, updated the image in step 3 of each topic.
  • In the Generating the EMIF Design Example for Simulation topic, updated the Generated Simulation Design Example File Structure figure and modified the note following the figure.
  • In the Generating the Synthesizable EMIF Design Example topic, added a step and a figure for multiple interfaces.
2019.07.31 19.2 1.2.0
  • Added About the External Memory Interfaces Intel® Agilex™ FPGA IP chapter and Release Information.
  • Updated dates and version numbers.
  • Minor enhancement to the Synthesis Design Example figure in the Synthesis Design Example topic.
2019.04.02 19.1  
  • Initial release.
Level Two Title