HDMI Intel® Arria 10 FPGA IP Design Example User Guide

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ID 683156
Date 7/29/2022
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Document Table of Contents
Document Table of Contents x
1. HDMI Intel® FPGA IP Design Example Quick Start Guide for Intel® Arria® 10 Devices 2. HDMI 2.1 Design Example (Support FRL = 1) 3. HDMI 2.0 Design Example (Support FRL = 0) 4. HDCP Over HDMI 2.0/2.1 Design Example 5. HDMI Intel® Arria® 10 FPGA IP Design Example User Guide Archives 6. Revision History for HDMI Intel® Arria® 10 FPGA IP Design Example User Guide
1. HDMI Intel® FPGA IP Design Example Quick Start Guide for Intel® Arria® 10 Devices x
1.1. Generating the Design 1.2. Simulating the Design 1.3. Compiling and Testing the Design 1.4. HDMI Intel® FPGA IP Design Example Parameters
2. HDMI 2.1 Design Example (Support FRL = 1) x
2.1. HDMI 2.1 RX-TX Retransmit Design Block Diagram 2.2. Creating RX-Only or TX-Only Designs 2.3. Hardware and Software Requirements 2.4. Directory Structure 2.5. Design Components 2.6. Dynamic Range and Mastering (HDR) InfoFrame Insertion and Filtering 2.7. Design Software Flow 2.8. Running the Design in Different FRL Rates 2.9. Clocking Scheme 2.10. Interface Signals 2.11. Design RTL Parameters 2.12. Hardware Setup 2.13. Simulation Testbench 2.14. Design Limitations 2.15. Debugging Features 2.16. Upgrading Your Design
2.5. Design Components x
2.5.1. HDMI TX Components 2.5.2. HDMI RX Components 2.5.3. Top-Level Common Blocks
2.15. Debugging Features x
2.15.1. Software Debugging Message 2.15.2. SCDC Information from the Sink Connected to TX 2.15.3. Clock Frequency Measurement
3. HDMI 2.0 Design Example (Support FRL = 0) x
3.1. HDMI 2.0 RX-TX Retransmit Design Block Diagram 3.2. Hardware and Software Requirements 3.3. Directory Structure 3.4. Design Components 3.5. Dynamic Range and Mastering (HDR) InfoFrame Insertion and Filtering 3.6. Clocking Scheme 3.7. Interface Signals 3.8. Design RTL Parameters 3.9. Hardware Setup 3.10. Simulation Testbench 3.11. Upgrading Your Design
4. HDCP Over HDMI 2.0/2.1 Design Example x
4.1. High-bandwidth Digital Content Protection (HDCP) 4.2. Nios II Processor Software Flow 4.3. Design Walkthrough 4.4. Protection of Encryption Key Embedded in FPGA Design 4.5. Security Considerations 4.6. Debug Guidelines
4.1. High-bandwidth Digital Content Protection (HDCP) x
4.1.1. HDCP Over HDMI Design Example Architecture
4.3. Design Walkthrough x
4.3.1. Set Up the Hardware 4.3.2. Generate the Design 4.3.3. Include HDCP Production Keys 4.3.4. Compile the Design 4.3.5. View the Results
4.3.3. Include HDCP Production Keys x
4.3.3.1. Store plain HDCP production keys in the FPGA (Support HDCP Key Management = 0) 4.3.3.2. Store encrypted HDCP production keys in the external flash memory or EEPROM (Support HDCP Key Management = 1)
4.3.3.1. Store plain HDCP production keys in the FPGA (Support HDCP Key Management = 0) x
4.3.3.1.1. HDCP Key Mapping from DCP Key Files 4.3.3.1.2. hdcp1x_tx_kmem.v and hdcp1x_rx_kmem.v files 4.3.3.1.3. hdcp2x_rx_kmem.v file 4.3.3.1.4. hdcp2x_tx_kmem.v file
4.3.3.2. Store encrypted HDCP production keys in the external flash memory or EEPROM (Support HDCP Key Management = 1) x
4.3.3.2.1. Intel KEYENC 4.3.3.2.2. Key Programmer
4.3.5. View the Results x
4.3.5.1. Push Buttons and LED Functions
4.6. Debug Guidelines x
4.6.1. HDCP Status Signals 4.6.2. Modifying HDCP Software Parameters 4.6.3. Frequently Asked Questions (FAQ)
1. HDMI Intel® FPGA IP Design Example Quick Start Guide for Intel® Arria® 10 Devices
2. HDMI 2.1 Design Example (Support FRL = 1)
3. HDMI 2.0 Design Example (Support FRL = 0)
4. HDCP Over HDMI 2.0/2.1 Design Example
5. HDMI Intel® Arria® 10 FPGA IP Design Example User Guide Archives
6. Revision History for HDMI Intel® Arria® 10 FPGA IP Design Example User Guide

4.3.5.1. Push Buttons and LED Functions

Use the push buttons and LED functions on the board to control your demonstration.
Table 55.  Push Button and LED Indicators (SUPPORT FRL = 0)
Push Button/LED Functions
cpu_resetn Press once to perform system reset.
user_pb[0] Press once to toggle the HPD signal to the standard HDMI source.
user_pb[1]
  • Press and hold to instruct the TX core to send the DVI encoded signal.
  • Release to send the HDMI encoded signal.
  • Make sure the incoming video is in 8 bpc RGB color space.
user_pb[2]
  • Press and hold to instruct the TX core to stop sending the InfoFrames from the sideband signals.
  • Release to resume sending the InfoFrames from the sideband signals.

user_led[0]

 RX HDMI PLL lock status.
  • 0: Unlocked
  • 1: Locked

user_led[1]

 RX HDMI core lock status
  • 0: At least 1 channel unlocked
  • 1: All 3 channels locked

user_led[2]

 RX HDCP1x IP decryption status.
  • 0: Inactive
  • 1: Active

user_led[3]

 RX HDCP2x IP decryption status.
  • 0: Inactive
  • 1: Active

user_led[4]

 TX HDMI PLL lock status.
  • 0: Unlocked
  • 1: Locked

user_led[5]
TX transceiver PLL lock status.
  • 0: Unlocked
  • 1: Locked

user_led[6]

 TX HDCP1x IP encryption status.
  • 0: Inactive
  • 1: Active

user_led[7]

 TX HDCP2x IP encryption status.
  • 0: Inactive
  • 1: Active
Table 56.  Push Button and LED Indicators (SUPPORT FRL = 1)
Push Button/LED Functions
cpu_resetn Press once to perform system reset.
user_dipsw

User-defined DIP switch to toggle the passthrough mode.

  • OFF (default position) = Passthrough

    HDMI RX on the FPGA gets the EDID from external sink and presents it to the external source it is connected to.

  • ON = You may control the RX maximum FRL rate from the Nios® II terminal. The command modifies the RX EDID by manipulating the maximum FRL rate value.

Refer to Running the Design in Different FRL Rates for more information about setting the different FRL rates.

user_pb[0] Press once to toggle the HPD signal to the standard HDMI source.
user_pb[1] Reserved.
user_pb[2] Press once to read the SCDC registers from the sink connected to the TX of the Bitec HDMI 2.1 FMC daughter card.
Note: To enable read, you must set DEBUG_MODE to 1 in the software.
user_led_g[0] RX FRL clock PLL lock status.
  • 0: Unlocked
  • 1: Locked
user_led_g[1] RX HDMI video lock status.
  • 0: Unlocked
  • 1: Locked
user_led_g[2] RX HDCP1x IP decryption status.
  • 0: Inactive
  • 1: Active
user_led_g[3] RX HDCP2x IP decryption status.
  • 0: Inactive
  • 1: Active
user_led_g[4] TX FRL clock PLL lock status.
  • 0: Unlocked
  • 1: Locked
user_led_g[5] TX HDMI video lock status.
  • 0 = Unlocked
  • 1 = Locked
user_led_g[6] TX HDCP1x IP encryption status.
  • 0: Inactive
  • 1: Active
user_led_g[7]
TX HDCP2x IP encryption status.
  • 0: Inactive
  • 1: Active
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