HDMI Intel® Arria 10 FPGA IP Design Example User Guide

ID 683156
Date 7/29/2022
Public
Document Table of Contents

1.4. HDMI Intel® FPGA IP Design Example Parameters

Table 2.   HDMI Intel® FPGA IP Design Example Parameters for Intel® Arria® 10 DevicesThese options are available for Intel® Arria® 10 devices only.

Parameter

Value

Description

Available Design Example

Select Design

Arria 10 HDMI RX-TX Retransmit

Select the design example to be generated.
Design Example Files
Simulation On, Off Turn on this option to generate the necessary files for the simulation testbench.
Synthesis On, Off Turn on this option to generate the necessary files for Intel® Quartus® Prime compilation and hardware demonstration.

Generated HDL Format

Generate File Format Verilog, VHDL Select your preferred HDL format for the generated design example fileset.
Note: This option only determines the format for the generated top level IP files. All other files (e.g. example testbenches and top level files for hardware demonstration) are in Verilog HDL format.

Target Development Kit

Select Board

No Development Kit,

Arria 10 GX FPGA Development Kit,

Custom Development Kit

Select the board for the targeted design example.
  • No Development Kit: This option excludes all hardware aspects for the design example. The IP core sets all pin assignments to virtual pins.
  • Arria 10 GX FPGA Development Kit : This option automatically selects the project's target device to match the device on this development kit. You may change the target device using the Change Target Device parameter if your board revision has a different device variant. The IP core sets all pin assignments according to the development kit.
  • Custom Development Kit: This option allows the design example to be tested on a third party development kit with an Intel FPGA. You may need to set the pin assignments on your own.
Target Device
Change Target Device On, Off Turn on this option and select the preferred device variant for the development kit.

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