HDMI Intel® Arria 10 FPGA IP Design Example User Guide

ID 683156
Date 7/29/2022
Public
Document Table of Contents

1.3. Compiling and Testing the Design

To compile and run a demonstration test on the hardware example design, follow these steps:
  1. Ensure hardware example design generation is complete.
  2. Launch the Intel® Quartus® Prime software and open the .qpf file.
    • HDMI 2.1 design example with Support FRL enabled: project directory/quartus/a10_hdmi21_frl_demo.qpf
    • HDMI 2.0 design example with Support FRL disabled: project directory/quartus/a10_hdmi2_demo.qpf
  3. Click Processing > Start Compilation.
  4. After successful compilation, a .sof file will be generated in the quartus/output_files directory.
  5. Connect to the on-board FMC port B (J2):
    • HDMI 2.1 design example with Support FRL enabled: Bitec HDMI 2.1 FMC Daughter Card Rev 9
    • HDMI 2.0 design example with Support FRL disabled: Bitec HDMI 2.0 FMC Daughter Card Rev 11
  6. Connect TX (P1) of the Bitec FMC daughter card to an external video source.
  7. Connect RX (P2) of the Bitec FMC daughter card to an external video sink or video analyzer.
  8. Ensure all switches on the development board are in default position.
  9. Configure the selected Intel® Arria® 10 device on the development board using the generated .sof file (Tools > Programmer ).
  10. The analyzer should display the video generated from the source.

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