HDMI Intel® Arria 10 FPGA IP Design Example User Guide

ID 683156
Date 7/29/2022

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Document Table of Contents

1.1. Generating the Design

Use the HDMI Intel® FPGA IP parameter editor in the Intel® Quartus® Prime software to generate the design examples.

Starting with the Nios® II EDS in the Intel® Quartus® Prime Pro Edition software version 19.2 and Intel® Quartus® Prime Standard Edition software version 19.1, Intel has removed the Cygwin component in the Windows* version of Nios II EDS, replacing it with Windows* Subsytem for Linux (WSL). If you are a Windows* user, you need to install WSL prior to generating your design example.

Figure 2. Generating the Design Flow
  1. Create a project targeting Intel® Arria® 10 device family and select the desired device.
  2. In the IP Catalog, locate and double-click Interface Protocols > Audio & Video > HDMI Intel® FPGA IP . The New IP Variant or New IP Variation window appears.
  3. Specify a top-level name for your custom IP variation. The parameter editor saves the IP variation settings in a file named <your_ip>.ip or <your_ip>.qsys.
  4. Click OK. The parameter editor appears.
  5. On the IP tab, configure the desired parameters for both TX and RX.
  6. Turn on the Support FRL parameter to generate the HDMI 2.1 design example in FRL mode. Turn it off to generate the HDMI 2.0 design example without FRL.
  7. On the Design Example tab, select Arria 10 HDMI RX-TX Retransmit.
  8. Select Simulation to generate the testbench, and select Synthesis to generate the hardware design example.
    You must select at least one of these options to generate the design example files. If you select both, the generation time is longer.
  9. For Generate File Format, select Verilog or VHDL.
  10. For Target Development Kit, select Intel® Arria® 10 GX FPGA Development Kit. If you select a development kit, then the target device (selected in step 4) changes to match the device on target board. For Intel® Arria® 10 GX FPGA Development Kit, the default device is 10AX115S2F4I1SG.
  11. Click Generate Example Design.