2.5.1. HDMI TX Components
|HDMI TX Core||
The IP receives video data from the top level and performs auxiliary data encoding, audio data encoding, video data encoding, scrambling, TMDS encoding or packetization.
|IOPLL||The IOPLL (iopll_frl) generates the FRL clock for the TX core. This reference clock receives the TX FPLL output clock.
FRL clock frequency = Data rate per lanes x 4 / (FRL characters per clock x 18)
|Transceiver PHY Reset Controller||
The Transceiver PHY reset controller ensures a reliable initialization of the TX transceivers. The reset input of this controller is triggered from the top level, and it generates the corresponding analog and digital reset signal to the Transceiver Native PHY block according to the reset sequencing inside the block.
The tx_ready output signal from this block also functions as a reset signal to the HDMI Intel® FPGA IP to indicate the transceiver is up and running, and ready to receive data from the core.
|Transceiver Native PHY||
Hard transceiver block that receives the parallel data from the HDMI TX core and serializes the data from transmitting it.
Note: To meet the HDMI TX inter-channel skew requirement, set the TX channel bonding mode option in the Intel® Arria® 10 Transceiver Native PHY parameter editor to PMA and PCS bonding. You also need to add the maximum skew (set_max_skew) constraint requirement to the digital reset signal from the transceiver reset controller (tx_digitalreset) as recommended in the Intel® Arria® 10 Transceiver PHY User Guide.
The transmitter PLL block provides the serial fast clock to the Transceiver Native PHY block. For this HDMI Intel® FPGA IP design example, fPLL is used as TX PLL.
TX PLL has two reference clocks.
|TX Reconfiguration Management||
|Output buffer||This buffer acts as an interface to interact the I2C interface of the HDMI DDC and redriver components.|
|Mode||Data Rate||Oversampler 1 (2x oversample)||Oversampler 2 (4x oversample)||Oversample Factor||Oversampled Data Rate (Mbps)|
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