HDMI Intel® Arria 10 FPGA IP Design Example User Guide

ID 683156
Date 7/29/2022
Public
Document Table of Contents

3. HDMI 2.0 Design Example (Support FRL = 0)

The HDMI Intel® FPGA IP design example demonstrates one HDMI instance parallel loopback comprising three RX channels and four TX channels.
Table 28.   HDMI Intel® FPGA IP Design Example for Intel® Arria® 10 Devices
Design Example Data Rate Channel Mode Loopback Type

Arria 10 HDMI RX-TX Retransmit

< 6,000 Mbps Simplex Parallel with FIFO buffer

Features

  • The design instantiates FIFO buffers to perform a direct HDMI video stream passthrough between the HDMI sink and source.
  • The design uses LED status for early debugging stage.
  • The design comes with RX and TX only options.
  • The design demonstrates the insertion and filtering of Dynamic Range and Mastering (HDR) InfoFrame in RX-TX link module.
  • The design demonstrates the management of EDID passthrough from an external HDMI sink to an external HDMI source when triggered by a TX hot-plug event.
  • The design allows run-time control through DIP switch and push-button to manage the HDMI TX core signals:
    • mode signal to select DVI or HDMI encoded video frame
    • info_avi[47], info_vsi[61], and audio_info_ai[48] signals to select auxiliary packet transmission through sidebands or auxiliary data ports

The RX instance receives a video source from the external video generator, and the data then goes through a loopback FIFO before it is transmitted to the TX instance. You need to connect an external video analyzer, monitor, or a television with HDMI connection to the TX core to verify the functionality.

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