GPIO Intel® FPGA IP User Guide: Intel® Arria® 10 and Intel® Cyclone® 10 GX Devices

ID 683136
Date 7/15/2021
Public

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Single Data Rate Input Register

Figure 13. Single Data Rate Input Register


Table 14.  Single Data Rate Input Register .sdc Command Examples
Command Command Example Description
create_clock create_clock -name sdr_in_clk -period "100 MHz" sdr_in_clk Creates clock setting for the input clock.
set_input_delay set_input_delay -clock sdr_in_clk 0.15 sdr_in_data Instructs the Timing Analyzer to analyze the timing of the input I/O with a 0.15 ns input delay.