GPIO Intel® FPGA IP User Guide: Intel® Arria® 10 and Intel® Cyclone® 10 GX Devices

ID 683136
Date 7/15/2021

A newer version of this document is available. Customers should click here to go to the newest version.

Document Table of Contents

GPIO Intel® FPGA IP Features

The GPIO IP core includes features to support the device I/O blocks. You can use the Intel® Quartus® Prime parameter editor to configure the GPIO IP core.

The GPIO IP core provides these components:

  • Double data rate input/output (DDIO)—a digital component that doubles or halves the data rate of a communication channel.
  • Delay chains—configure the delay chains to perform specific delay and assist in I/O timing closure.
  • I/O buffers—connect the pads to the FPGA.