GPIO Intel® FPGA IP User Guide: Intel® Arria® 10 and Intel® Cyclone® 10 GX Devices

ID 683136
Date 7/15/2021
Public

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Timing Closure Guidelines

For the GPIO input registers, the input I/O transfer is likely to fail the hold time if you do not set the input delay chain. This failure is caused by the clock delay being larger than the data delay.

To meet the hold time, add delay to the input data path using the input delay chain. In general, the input delay chain is around 60 ps per step at the –1 speed grade. To get an approximate input delay chain setting to pass the timing, divide the negative hold slack by 60 ps.

However, if the I/O PLL drives the clocks of the GPIO input registers (simple register or DDIO mode), you can set the compensation mode to source synchronous mode. The Fitter will attempt to configure the I/O PLL for a better setup and hold slack for the input I/O timing analysis.

For the GPIO output and output enable registers, you can add delay to the output data and clock using the output and output enable delay chains.

  • If you observe setup time violation, you can increase the output clock delay chain setting.
  • If you observe hold time violation, you can increase the output data delay chain setting.

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