GPIO Intel® FPGA IP User Guide: Intel® Arria® 10 and Intel® Cyclone® 10 GX Devices

ID 683136
Date 7/15/2021
Public

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Delay Elements

The Intel® Quartus® Prime software does not automatically set delay elements to maximize slack in the I/O timing analysis. To close the timing or maximize slack, set the delay elements manually in the Intel® Quartus® Prime settings file (.qsf).
Table 13.  Delay Elements .qsf AssignmentsSpecify these assignments in the .qsf to access the delay elements.
Delay Element .qsf Assignment
Input Delay Element set_instance_assignment –to <PIN> -name INPUT_DELAY_CHAIN <0..63>
Output Delay Element set_instance_assignment –to <PIN> -name OUTPUT_DELAY_CHAIN <0..15>
Output Enable Delay Element set_instance_assignment –to <PIN> -name OE_DELAY_CHAIN <0..15>

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