GPIO Intel® FPGA IP User Guide: Intel® Arria® 10 and Intel® Cyclone® 10 GX Devices

ID 683136
Date 7/15/2021
Public

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Data Interface Signals and Corresponding Clocks

Table 8.  Data Interface Signals and Corresponding Clocks
Signal Name Parameter Configuration Clock
Register Mode Half Rate Separate Clocks  
din
  • Simple Register
  • DDIO
Off Off ck
DDIO On Off ck_hr
  • Simple Register
  • DDIO
Off On ck_in
DDIO On On ck_hr_in
  • dout
  • oe
  • Simple Register
  • DDIO
Off Off ck
DDIO On Off ck_hr
  • Simple Register
  • DDIO
Off On ck_out
DDIO On On ck_hr_out
  • sclr
  • sset
  • All pad signals
  • Simple Register
  • DDIO
Off Off ck
DDIO On Off ck_fr
  • Simple Register
  • DDIO
Off On
  • Input path: ck_in
  • Output path: ck_out
DDIO On On
  • Input path: ck_fr_in
  • Output path: ck_fr_out

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