GPIO Intel® FPGA IP User Guide: Intel® Arria® 10 and Intel® Cyclone® 10 GX Devices

ID 683136
Date 7/15/2021

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Document Table of Contents

Document Revision History for GPIO Intel® FPGA IP User Guide: Intel® Arria® 10 and Intel® Cyclone® 10 GX Devices

Document Version Intel® Quartus® Prime Version IP Version Changes
2021.07.15 21.2 20.0.0 Updated the diagram that shows the simplified view of the single-ended GPIO input path to update dout[0] to dout[3] and dout[3] to dout[0].
2021.03.29 21.1 20.0.0 Updated the GPIO IP version number to 20.0.0.
2021.03.12 20.4 19.3.0 Updated the IP migration guideline to specify that the GPIO IP drives datain_h on the rising edge and datain_l on the falling edge.
2019.10.01 19.3 19.3.0 Corrected typographical error in the .qsf assignment codes in the topic about delay elements.
2019.03.04 18.1 18.1 In the topics about the input path, and output and output enable paths:
2018.08.28 18.0 18.0
  • Retitled the document from Intel FPGA GPIO IP Core User Guide to GPIO Intel FPGA IP User Guide: Intel® Arria® 10 and Intel® Cyclone® 10 GX Devices.
  • Added a link to the Intel® Stratix® 10 GPIO IP user guide.
  • Renamed the IP from "Intel FPGA GPIO" to "GPIO Intel FPGA IP".
  • Corrected instances of "clk_fr" and "clk_hr" to "ck_fr" and "ck_hr".
  • Updated the GPIO IP input path and output paths diagrams to show the actual IP core signal names.
Date Version Changes
November 2017 2017.11.06
  • Added support for Intel® Cyclone® 10 GX devices.
  • Updated the signal names in figures to match the signal names in the GPIO IP core.
  • Added the output path waveform.
  • Renamed "Altera GPIO IP core" to "Intel FPGA GPIO IP core".
  • Renamed "Altera IOPLL IP core" to "Intel FPGA IOPLL IP core".
  • Renamed "TimeQuest Timing Analyzer" to "Timing Analyzer".
  • Renamed "Qsys" to "Platform Designer".
  • Clarified that the ASET and ACLR signals are active high.
May 2017 2017.05.08
  • Updated the table listing the GPIO buffer parameters to specify the conditions for the Use bus-hold circuitry parameter option.
  • Rebranded as Intel.
October 2016 2016.10.31
  • Updated the input path waveform.
  • Added a topic describing the high and low bits in the din and dout buses.
August 2016 2016.08.05
  • Added notes about dynamic OCT support in the GPIO IP core.
  • Updated the topic about parameter settings to improve accuracy and clarity.
  • Updated the section about generating the design example.
  • Added a guideline topic about behavior of the legacy ports when you migrate to the GPIO IP core from Stratix® V, Arria® V, and Cyclone® V devices.
  • Rewrote and restructured the document to improve clarity and for ease of reference.
  • Changed instances of Quartus II to Quartus Prime.
August 2014 2014.08.18
  • Added timing information.
  • Added register packing information.
  • Added Use legacy top-level port names parameter. This is a new parameter.
  • Added register packing information.
  • Replaced the term megafunction with IP core.
November 2013 2013.11.29 Initial release.