GPIO Intel® FPGA IP User Guide: Intel® Arria® 10 and Intel® Cyclone® 10 GX Devices

ID 683136
Date 7/15/2021
Public

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GPIO IP Core Synthesizable Intel® Quartus® Prime Design Example

The synthesizable design example is a compilation-ready Platform Designer system that you can include in an Intel® Quartus® Prime project.

Generating and Using the Design Example

To generate the synthesizable Intel® Quartus® Prime design example from the source files, run the following command in the design example directory:

quartus_sh -t make_qii_design.tcl

To specify an exact device to use, run the following command:

quartus_sh -t make_qii_design.tcl [device_name]

The TCL script creates a qii directory that contains the ed_synth.qpf project file. You can open and compile this project in the Intel® Quartus® Prime software.

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