AN 733: Altera JESD204B IP Core and TI ADC12J4000 Hardware Checkout Report

ID 683135
Date 2/09/2015
Public

1.7. Test Result Comments

In each test case, the RX JESD204B IP core successfully initialize from CGS phase, ILA phase, and until user data phase. The long transport layer test pattern (as defined in the JESD204B specification section 5.1.6.3) is observed at the data output of the RX transport layer.

In the deterministic measurement test case DL.3, the link clock count in the FPGA depends on the board layout. The link clock count may vary by only one link clock when you reset or power cycle the FPGA and ADC. The link clock variation in the deterministic latency measurement is caused by word alignment, where the control characters fall into the next cycle of the data some time after realignment. This makes the duration of ILAS phase longer by one link clock some time after a reset or power cycle.

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