AN 733: Altera JESD204B IP Core and TI ADC12J4000 Hardware Checkout Report

ID 683135
Date 2/09/2015
Public

1.4.1.2. Initial Frame and Lane Synchronization

Table 2.  Initial Frame and Lane Synchronization Test Cases

Test Case

Objective

Description

Passing Criteria

ILA.1

Check whether the initial frame synchronization state machine enters FS_DATA state upon receiving non /K/ characters.

The following signals in <ip_variant_name> _inst_phy.v are tapped:

  • jesd204_rx_pcs_data[(L*32)-1:0]
  • jesd204_rx_pcs_data_valid[L-1:0]
  • jesd204_rx_pcs_kchar_data[(L*4)-1:0] 2

The following signals in <ip_variant_name> .v are tapped:

  • rx_dev_sync_n
  • jesd204_rx_int

The rxlink_clk is used as the SignalTap II sampling clock.

Each lane is represented by a 32-bit data bus in the jesd204_rx_pcs_data signal. The 32-bit data bus for is divided into four octets.

  • /R/ character or K28.0 (0x1C) is observed after the /K/ character at the jesd204_rx_pcs_data bus.
  • The jesd204_rx_pcs_data_valid signal must be asserted to indicate that data from the PCS is valid.
  • The rx_dev_sync_n and jesd204_rx_int signals are deasserted.
  • Each multiframe in the ILAS phase ends with a /A/ character or K28.3 (0x7C).
  • The jesd204_rx_pcs_kchar_data signal is asserted whenever control characters like /K/, /R/, /Q/, or /A/ characters are observed.

ILA.2

Check the JESD204B configuration parameters from ADC in second multiframe.

The following signals in <ip_variant_name> _inst_phy.v are tapped:

  • jesd204_rx_pcs_data[(L*32)-1:0]
  • jesd204_rx_pcs_data_valid[L-1:0] 2

The following signal in <ip_variant_name> .v is tapped:

  • jesd204_rx_int

The rxlink_clk is used as the SignalTap II sampling clock.

The system console accesses the following registers:

  • ilas_octet0
  • ilas_octet1
  • ilas_octet2
  • ilas_octet3

The content of 14 configuration octets in the second multiframe is stored in these 32-bit registers ( ilas_octet0, ilas_octet1, ilas_octet2, and ilas_octet3).

  • /R/ character is followed by /Q/ character or K28.4 (0x9C) at the beginning of second multiframe.
  • The jesd204_rx_int signal is deasserted if there is no error.
  • Octets 0–13 read from these registers match with the JESD204B parameters in each test setup.

ILA.3

Check the lane alignment

The following signals in <ip_variant_name> _inst_phy.v are tapped:

  • jesd204_rx_pcs_data[(L*32)-1:0]
  • jesd204_rx_pcs_data_valid[L-1:0] 2

The following signals in <ip_variant_name> .v are tapped:

  • rx_somf[3:0]
  • dev_lane_aligned
  • jesd204_rx_int

The rxlink_clk is used as the SignalTap II sampling clock.

  • The dev_lane_aligned signal is asserted upon the last /A/ character of the ILAS is received, which is followed by the first data octet.
  • The rx_somf marks the start of multiframe in user data phase.
  • The jesd204_rx_int signal is deasserted if there is no error.
2 L indicates the number of lanes.

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