AN 733: Altera JESD204B IP Core and TI ADC12J4000 Hardware Checkout Report

ID 683135
Date 2/09/2015
Public

1.3. ADC12J4000 EVM Software Setup

The ADC12J4000 EVM software configures the ADC12J4000 device, LMX2581 frequency synthesizer and LMK04828 clock generator for JESD204B link operation. Setup files for each of the parameter configuration are included in the software installation.

You need to configure the ADC12J4000, LMX2581, and LMK04828 modules with the correct settings and sequence for the JESD204B link to operate at the targeted data rate and JESD204B link parameters. Follow these steps to set up the configuration via the ADC12J4000 EVM graphical user interface (GUI):

  1. Configure the FPGA.
  2. A number of changes are required in the default setup files of the ADC and LMK04828 devices. These are the setup files used for the various JESD204B modes:
    • LMF=124 mode uses LMK04828_DB16_DDR_P54_Fs_3500Msps.cfg & ADC12J4000_DB16_DDR_P54.cfg
    • LMF=222 mode uses LMK04828_DB8_DDR_P54_Fs_3500Msps.cfg & ADC12J4000_DB8_DDR_P54.cfg
    • LMF=422 mode uses LMK04828_DB4_DDR_P54_Fs_3500Msps.cfg & ADC12J4000_DB4_DDR_P54.cfg
  3. Modify the setup files:

    For LMK04828,

    • 0x113 0x11 //set the analog delay properties for the device clock
    • 0x114 0x42 //set the FPGA device clock half step value
    • 0x117 0x04 //set output format HSDS 10mA of the device clock
    • 0x12E 0xF0 //set sysref active in normal mode
    • SYSREF divider value for various mode:
      • For LMF=222,422 (K=32): 0x13A 0x00, 0x13B 0x80  //set the value of SYSREF output divider =128
      • For LMF=124 (K=32,16): 0x13A 0x01, 0x13B 0x00  //set the value of SYSREF output divider = 256
      • For LMF=222,422 (K=16): 0x13A 0x00, 0x13B 0x40  // set the value of SYSREF output divider = 64
    • 0x140 0x00 //power on sysref pulse generator

    Set the following programming sequence at the end of the LMK04828 default setup file:

    • 0x143 0x11 //set SYNC_MUX to "Pin" as part of sysref/clock dividers initialize sequence
    • 0x139 0x00 //set SYSREF_Mux to "Normal" as part of sysref/clock dividers initialize sequence
    • 0x143 0x31 //toggle sync_pol bit
    • 0x143 0x11 //toggle sync_pol bit
    • 0x144 0xFF //disable syncing of all clock outputs
    • 0x139 0x03 //continuous SYSREF mode

    For ADC12J4000,

    • 0x0030 0xF0 // SYSREF receiver and processor on, clear sysref detection, clear dirty capture, DC-coupled SYSREF & Device clock
    • 0x0030 0xC0 // SYSREF receiver and processor on, DC-coupled SYSREF & Device clock
    • 0x0201 0xFE // Scrambler on, KM1 = 31, DDR, JESD disabled
    • 0x0202 0x85 // P54 PLL on, Single-ended SYNC, Long transport layer test mode
    • 0x0201 0xFF // Scrambler on, KM1 = 31, DDR, JESD enabled
  4. Save the setup files in these two locations:
    • <EVM GUI installation folder>\Texas Instruments\ADC12J4000EVM GUI\Configuration Files
    • <EVM GUI installation folder>\Texas Instruments\ADC12J4000EVM GUI v1.1\Configuration Files
  5. In the User Inputs section of the ADC12J4000 EVM GUI,
    1. At the #1. Clock Source drop-down list, select On-board option.
    2. At the #2a. On-board Fs Selection drop-down list, select Fs = 3760 Msps.
    3. At the #3. Decimation and Serial Data Mode drop-down list,
      • Select Decimate-by-16; DDR; P54 for LMF=124 mode
      • Select Decimate-by-8; DDR; P54 for LMF=222 mode
      • Select Decimate-by-4; DDR; P54 for LMF=422 mode
    4. Click the Program Clocks and ADC button.

The following figures shows the software setup GUI for LMF=422 configuration.

Figure 3. ADC12J4000 EVM Software Setup - EVM


Figure 4. ADC12J4000 EVM Software Setup - JESD204B / DDC


Figure 5. ADC12J4000 EVM Software Setup - Low Level View


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