AN 733: Altera JESD204B IP Core and TI ADC12J4000 Hardware Checkout Report

ID 683135
Date 2/09/2015
Public

1.4.4. Deterministic Latency (Subclass 1)

The LMK04828 system clock generator generates periodic SYSREF pulse for both the ADC12J4000 and JESD204B IP core. The SYSREF pulse restarts the LMF counter and realigns it to the LMFC boundary.

Figure 6.  Deterministic Latency Measurement Timing Diagram


The JESD204B IP core and ADC are configured to operate in continuous SYSREF detection mode.

Table 5.  Deterministic Latency Test Cases

Test Case

Objective

Description

Passing Criteria

DL.1

Check the FPGA SYSREF continuous detection.

Check that the FPGA detects the first rising edge of SYSREF pulse and SYSREF period is correct.

Read the status of csr_sysref_singledet (bit[2]) identifier in the syncn_sysref_ctrl register at address 0x54.

Read the status of csr_sysref_lmfc_err (bit[1]) identifier in the rx_err0 register at address 0x60.

The value of sysref_singledet identifier should be zero.

The value of csr_sysref_lmfc_err identifier should be zero.

DL.2

Check the SYSREF capture.

Check that FPGA and ADC capture SYSREF correctly and restart the LMF counter for every reset and power cycle.

Read the value of rbd_count (bit[10:3]) identifier in the rx_status0 register at address 0x80.

If the SYSREF is captured correctly and the LMF counter restarts, for every reset and power cycle, the rbd_count value should only vary by two integers due to the word alignment.

DL.3

Check the latency from start of SYNC~ deassertion to the first user data output.

Check that the latency is fixed for every FPGA and ADC reset and power cycle.

Record the number of link clocks count from the start of SYNC~ deassertion to the first user data output, which is the assertion of the jesd204_rx_link_valid signal. The deterministic latency measurement block has a counter to measure the link clock count.

Consistent latency from the start of SYNC~ deassertion to the assertion of the jesd204_rx_link_valid signal.

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