AN 733: Altera JESD204B IP Core and TI ADC12J4000 Hardware Checkout Report

ID 683135
Date 2/09/2015
Public

1.4.1. Receiver Data Link Layer

This test area covers the test cases for code group synchronization (CGS) and initial frame and lane synchronization.

On link start up, the receiver issues a synchronization request and the transmitter transmits /K/ (K28.5) characters. The SignalTap II Logic Analyzer tool monitors the receiver data link layer operation.

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