AN 733: Altera JESD204B IP Core and TI ADC12J4000 Hardware Checkout Report

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ID 683135
Date 2/09/2015
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Document Table of Contents x
1. Altera JESD204B IP Core and TI ADC12J4000 Hardware Checkout Report
1. Altera JESD204B IP Core and TI ADC12J4000 Hardware Checkout Report x
1.1. Hardware Requirements 1.2. Hardware Setup 1.3. ADC12J4000 EVM Software Setup 1.4. Hardware Checkout Methodology 1.5. JESD204B IP Core and ADC Configurations 1.6. Test Results 1.7. Test Result Comments 1.8. AN 733 Document Revision History
1.4. Hardware Checkout Methodology x
1.4.1. Receiver Data Link Layer 1.4.2. Receiver Transport Layer 1.4.3. Descrambling 1.4.4. Deterministic Latency (Subclass 1)
1.4.1. Receiver Data Link Layer x
1.4.1.1. Code Group Synchronization (CGS) 1.4.1.2. Initial Frame and Lane Synchronization
1. Altera JESD204B IP Core and TI ADC12J4000 Hardware Checkout Report

1.6. Test Results

The following table contains the possible results and their definition.

Table 7.  Results Definition

Result

Definition

PASS

The Device Under Test (DUT) was observed to exhibit conformant behavior.

PASS with comments

The DUT was observed to exhibit conformant behavior. However, an additional explanation of the situation is included, such as due to time limitations only a portion of the testing was performed.

FAIL

The DUT was observed to exhibit non-conformant behavior.

Warning

The DUT was observed to exhibit behavior that is not recommended.

Refer to comments

From the observations, a valid pass or fail could not be determined. An additional explanation of the situation is included.

The following table shows the results for test cases CGS.1, CGS.2, ILA.1, ILA.2, ILA.3, TL.1, and SCR.1 with different values of L, M, F, K, SCR, sampling clock, and SYSREF frequencies.

Table 8.  Test Results for Test Cases CGS.1, CGS.2, ILA.1, ILA.2, ILA.3, TL.1, and SCR.1

Test

L

M

F

Subclass

SCR

K

Data Rate (Mbps)

Sampling Clock (MHz)

Link Clock (MHz)

Sysref Pulse Frequency (MHz)

Result

1

1

2

4

1

0

16

9400

235

235

7.34375

Pass

2

1

2

4

1

1

16

9400

235

235

7.34375

Pass

3

1

2

4

1

0

32

9400

235

235

7.34375

Pass

4

1

2

4

1

1

32

9400

235

235

7.34375

Pass

5

2

2

2

1

0

16

9400

470

235

29.375

Pass

6

2

2

2

1

1

16

9400

470

235

29.375

Pass

7

2

2

2

1

0

32

9400

470

235

14.6875

Pass

8

2

2

2

1

1

32

9400

470

235

14.6875

Pass

9

4

2

2

1

0

16

9400

940

235

29.375

Pass

10

4

2

2

1

1

16

9400

940

235

29.375

Pass

11

4

2

2

1

0

32

9400

940

235

14.6875

Pass

12

4

2

2

1

1

32

9400

940

235

14.6875

Pass

Table 9.  Test Results For Deterministic Latency Test

Test

L

M

F

Subclass

K

Data Rate (Mbps)

Sampling Clock (MHz)

Link Clock (MHz)

Result

DL.1

1

2

4

1

32

9400

235

235

Pass

DL.2

1

2

4

1

32

9400

235

235

Pass

DL.3

1

2

4

1

32

9400

235

235

Pass with comments.

Link clock observed = 191 with IP core csr_rbd_offset set to 0x04.

DL.1

2

2

2

1

32

9400

470

235

Pass

DL.2

2

2

2

1

32

9400

470

235

Pass

DL.3

2

2

2

1

32

9400

470

235

Pass with comments.

Link clock observed = 111 with IP core csr_rbd_offset set to 0x04.

DL.1

4

2

2

1

32

9400

940

235

Pass

DL.2

4

2

2

1

32

9400

940

235

Pass

DL.3

4

2

2

1

32

9400

940

235

Pass with comments.

Link clock observed = 111 with IP core csr_rbd_offset set to 0x04.

Level Two Title