SDI II Intel® FPGA IP User Guide

ID 683133
Date 6/28/2022
Public

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5.4.6.3. YCbCr 422 Pixel Packing

The Intel FPGA streaming video protocol specifies a packing scheme for YCbCr 422 pixels.

YCbCr 422 video packets must be an even number of pixels in length to ensure complete pairs of chroma information are transported. The following figure illustrates the 12 bits YCbCr 422 video packet transported over AXI4-Stream Video interface configured at Bits per color sample parameter set to 12 bits. Each pixel must be byte aligned when packing multiple pixels in parallel. In the example of 3 color planes per pixel and Bits per color sample set to 12 bits, each pixel (36 bits) does not perfectly fill a given number of bytes, hence additional 4 undefined bits are padded at the most significant bits of each pixel. The unused third color sample for each pixel are also padded with undefined data.

Figure 40. 12 Bits YCbCr 422 Video Packet When Parameter Bits Per Color Sample = 12

The following figure illustrates the 10 bits YCbCr 422 video packet transported over AXI4-Stream Video interface configured at IP parameter Bits per color sample parameter set to 12 bits. The active bits per color sample is less than the compile time parameter, hence the 2 least significant bits for each color sample are padded with zero.

Figure 41. 10 Bits YCbCr 422 Video Packet When Parameter Bits Per Color Sample = 12

In the following example of 3 color planes per pixel and Bits per color sample parameter set to 10 bits, each pixel (30 bits) does not perfectly fill a given number of bytes, hence additional 2 undefined bits are padded at the most significant bits of each pixel. The unused third color sample for each pixel are also padded with undefined data.

Figure 42. 10 Bits YCbCr 422 Video Packet When Parameter Bits Per Color Sample = 10

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