2.2. Device Family Support
|Device Family||Support Level|
|Intel® Agilex™ F-tile (from Intel® Quartus® Prime Pro Edition version 21.4 onwards)1||Preliminary|
|Intel® Stratix® 10—L-tile (from Intel® Quartus® Prime Pro Edition version 19.1 onwards)||Final|
|Intel® Stratix® 10—H-tile (from Intel® Quartus® Prime Pro Edition version 17.1 onwards)||Final|
|Intel® Cyclone® 10 GX (from Intel® Quartus® Prime Pro Edition version 17.1.1 onwards)||Final|
|Intel® Arria® 10 (from Intel® Quartus® Prime version 14.0A10 onwards)||Final|
|Arria V GZ and Cyclone V (from Intel® Quartus® Prime Standard Edition version 13.0 onwards)||Final|
|Arria V GX/GT/SX/ST and Stratix V (from Intel® Quartus® Prime Standard Edition version 12.1 onwards)||Final|
The following terms define device support levels for Intel FPGA IP cores:
- Advance support—the IP core is available for simulation and compilation for this device family. Timing models include initial engineering estimates of delays based on early post-layout information. The timing models are subject to change as silicon testing improves the correlation between the actual silicon and the timing models. You can use this IP core for system architecture and resource utilization studies, simulation, pinout, system latency assessments, basic timing assessments (pipeline budgeting), and I/O transfer strategy (data-path width, burst depth, I/O standards tradeoffs).
- Preliminary support—the IP core is verified with preliminary timing models for this device family. The IP core meets all functional requirements, but might still be undergoing timing analysis for the device family. It can be used in production designs with caution.
- Final support—the IP core is verified with final timing models for this device family. The IP core meets all functional and timing requirements for the device family and can be used in production designs.
Due to a problem in the Intel® Quartus® Prime Pro Edition Software v21.4, the SDI II Intel® Agilex™ F-Tile FPGA IP design example will fail at the Support-Logic Generation stage during compilation with the following error message:
"Error(21842): Support logic cannot be generated because IP components used in the design have conflicting settings."
For resolution, refer to KDB link: Why does the SDI II Intel Agilex F-Tile FPGA IP design example fail to compile at the Support-Logic Generation stage?.
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