SDI II Intel® FPGA IP User Guide

ID 683133
Date 6/28/2022
Public

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Document Table of Contents

5.1.1. Transmitter

The transmitter performs the following functions:

  • HD-SDI LN insertion
  • Sync bit insertion
  • HD-SDI CRC generation and insertion
  • Payload ID insertion
  • Matching timing reference signal (TRS) word
  • Clock enable signal generation
  • Scrambling and non-return-zero inverted (NRZI) coding

The block diagrams below illustrate the SDI II IP core transmitter (simplex) data path for each supported video standard.

For more information about the function of each submodule, refer to the Submodules section.

Figure 5. SD-SDI Transmitter Data Path Block Diagram


Figure 6. HD/3G-SDI Transmitter Data Path Block Diagram


Figure 7. Dual Rate SDI Transmitter Data Path Block Diagram


Figure 8. Dual Link HD-SDI Transmitter Data Path Block Diagram


Figure 9. Triple Rate SDI Transmitter Data Path Block Diagram


Figure 10. Multi Rate (up to 12G-SDI) Transmitter Data Path Block Diagram
Note: The transmit block shown in the diagram is the simplified version of the transmit block in the Triple Rate SDI Transmitter Data Path Block Diagram.

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