SDI II Intel® FPGA IP User Guide

ID 683133
Date 6/28/2022
Public

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7.1.3.3. TX EQ Settings

TX EQ settings on the transceiver can be tuned as per your design requirement to get a better signal integrity. The assignments for design example on Agilex I-Series SoC development kit must be set as below:

set_instance_assignment -name HSSI_PARAMETER "txeq_main_tap=47" -to <tx_serial_pin_name>

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