SDI II Intel® FPGA IP User Guide

ID 683133
Date 6/28/2022
Public

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7.1.3. Handling Transceiver in Intel® Agilex™ F-tile Devices

F-tile PMA/FEC Direct PHY Intel FPGA IP supports two clocking modes: the System PLL Clocking Mode and the Traditional PMA Clocking Mode.

Note: If you need to dynamically reconfigure the PHY, only System PLL clocking mode is supported.

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