SDI II Intel® FPGA IP User Guide

ID 683133
Date 6/28/2022
Public

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6.6. Receiver Streaming Video and Control Signals

Table 28.  Receiver Streaming Video Signals
Signal Width Clock Domain Direction Description
rx_axi4s_vid_out_tdata P tx_axi4s_clk Output AXI4-S data out.
rx_axi4s_vid_out_tvalid 1 tx_axi4s_clk Output AXI4-S data valid.
rx_axi4s_vid_out_tready 1 tx_axi4s_clk Input AXI4-S data ready.
rx_axi4s_vid_out_tlast 1 tx_axi4s_clk Output AXI4-S end of packet.
rx_axi4s_vid_out_tuser Q tx_axi4s_clk Output

AXI4-S tuser.

tuser[0] indicates start of video frame when asserted.

tuser[1] indicates the start of a non-video packet or metapacket when asserted.
Note:
  • P = max (16, floor[((bits per color sample x number of color planes) + 7) / 8] x pixels in parallel x 8) where bits per color sample = 10 or 12, number of color planes = 3 and pixels in parallel = 2.
  • Q = ceil (tdata width / 8)

Table 29.  Receiver Control Signals
Signal Width Clock Domain Direction Description
rx_av_mm_control_address 9 mgmt_clk Input Avalon memory-mapped control address.
rx_av_mm_control_write 1 mgmt_clk Input Avalon memory-mapped control write.
rx_av_mm_control_byteenable 4 mgmt_clk Input Avalon memory-mapped byte enable.
rx_av_mm_control_writedata 32 mgmt_clk Input Avalon memory-mapped write data.
rx_av_mm_control_read 1 mgmt_clk Input Avalon memory-mapped read.
rx_av_mm_control_readdata 32 mgmt_clk Output Avalon memory-mapped read data.
rx_av_mm_control_readdatavalid 1 mgmt_clk Output Avalon memory-mapped read data valid.
rx_av_mm_control_waitrequest 1 mgmt_clk Output Avalon memory-mapped wait request.

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