SDI II Intel® FPGA IP User Guide

ID 683133
Date 6/28/2022
Public

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7.1.2.3. Using Generated Reconfiguration Management for Triple and Multi Rates

You may encounter the following errors when you use the generated reconfiguration management block from the Intel® Quartus® Prime Standard Edition software:
  • Error (10161): Verilog HDL error at rcfg_sdi_cdr.sv: object "altera_xcvr_native_a10_reconfig_parameters_CFG0" is not declared. Verify the object name is correct. If the name is correct, declare the object.
  • Error (10161): Verilog HDL error at rcfg_sdi_cdr.sv: object "altera_xcvr_native_a10_reconfig_parameters_CFG1" is not declared. Verify the object name is correct. If the name is correct, declare the object.

The reconfiguration management block requires the CFG files that are generated from the transceiver to determine which registers to be reconfigured for data rate changes. However, the Intel® Quartus® Prime software cannot recognize these files outside of the transceiver library files.

To resolve this issue, add the library switch to the rcfg_sdi_cdr.sv file in your project’s .qsf.

set_global_assignment -name SYSTEMVERILOG_FILE <file hierarchy before the file>/rcfg_sdi_cdr.sv -library <phy_name_quartus_version>

  1. Find the exact library name that you should assign in the transceiver .qip file.
  2. Open the transceiver .qip file and search for the string: parameter_CFG0.
    You should see: set_global_assignment –library <phy_name_quartus_version> -name SYSTEMVERILOG_FILE ….CFG0.sv.

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