Stratix V Avalon-ST Interface for PCIe Solutions: User Guide

ID 683093
Date 5/03/2019
Document Table of Contents

5.14.4. Test Signals

Table 46.  Test Interface SignalsThe test_in bus provides run-time control and monitoring of the internal state of the IP core.






The bits of the test_in bus have the following definitions:

  • [0]: Simulation mode. This signal can be set to 1 to accelerate initialization by reducing the value of many initialization counters.
  • [1]: Reserved. Must be set to 1’b0
  • [2]: Descramble mode disable. This signal must be set to 1 during initialization in order to disable data scrambling. You can use this bit in simulation for Gen1 and Gen2 Endpoints and Root Ports to observe descrambled data on the link. Descrambled data cannot be used in open systems because the link partner typically scrambles the data.
  • [4:3]: Reserved. Must be set to 2’b01.
  • [5]: Compliance test mode. Disable/force compliance mode. When set, prevents the LTSSM from entering compliance mode. Toggling this bit controls the entry and exit from the compliance state, enabling the transmission of Gen1, Gen2 and Gen3 compliance patterns.
  • [6]: Forces entry to compliance mode when a timeout is reached in the state and not all lanes have detected their exit condition.
  • [7]: Disable low power state negotiation. Intel recommends setting this bit.
  • [31:8]: Reserved. Set to all 0s.

For more information about using the test_in to debug, refer to the Knowledge Base Solution How can I observe the Hard IP for PCI Express PIPE interface signals for Arria V GZ and Stratix V devices? in the Related Links below.

simu_pipe_mode Input When 1'b1, counter values are reduced to speed simulation.


When asserted, indicates accelerated initialization for simulation is active.



Lane Active Mode: This signal indicates the number of lanes that configured during link training. The following encodings are defined:
  • 4'b0001: 1 lane
  • 4'b0010: 2 lanes
  • 4'b:0100: 4 lanes
  • 4'b:1000: 8 lanes