2. Getting Started with the Stratix V Hard IP for PCI Express
This section provides instructions to help you quickly customize, simulate, and compile the Stratix V Hard IP for PCI Express IP Core. When you install the Quartus® Prime software you also install the IP Library. This installation includes design examples for Hard IP for PCI Express under the <install_dir>/ip/altera/altera_pcie/ directory.
After you install the Quartus® Prime software, you can copy the design examples from the <install_dir>/ip/altera/altera_pcie/altera_pcie/altera_pcie_hip_ast_ed/example_designs/<dev> directory. This walkthrough uses the Gen1 ×8 Endpoint, pcie_de_gen1_x8_ast128.qsys. The following figure illustrates the top‑level modules of the testbench in which the DUT, a Gen1 Endpoint, connects to a chaining DMA engine, labeled APPS in the following figure, and a Root Port model. The simulation can use the parallel PHY Interface for PCI Express (PIPE) or serial interface.
Intel provides example designs to help you get started with the Stratix V Hard IP for PCI Express IP Core. You can use example designs as a starting point for your own design. The example designs include scripts to compile and simulate the Stratix V Hard IP for PCI Express IP Core. This example design provides a simple method to perform basic testing of the Application Layer logic that interfaces to the Hard IP for PCI Express.
For a detailed explanation of this example design, refer to the Testbench and Design Example chapter. If you choose the parameters specified in this chapter, you can run all of the tests included in Testbench and Design Example chapter.
For more information about Qsys, refer to System Design with Qsys in the Quartus® Prime Handbook. For more information about the Qsys GUI, refer to About Qsys in Quartus® Prime Help.
Qsys Design Flow
Did you find the information on this page useful?