Stratix V Avalon-ST Interface for PCIe Solutions: User Guide

ID 683093
Date 5/03/2019
Document Table of Contents

3.2.1. Generating Synthesis Files

  1. On the Generate menu, select Generate HDL.
  2. For Create HDL design files for synthesis, select Verilog.
    You can leave the default settings for all other items.
  3. Click Generate to generate files for synthesis.
  4. Click Finish when the generation completes.