Stratix V Avalon-ST Interface for PCIe Solutions: User Guide

ID 683093
Date 5/03/2019
Document Table of Contents

2.1.4. Understanding the Files Generated

Table 7.  Overview of Qsys Generation Output Files




Includes the top‑level HDL file for the Hard IP for PCI Express and the .qip file that lists all of the necessary assignments and information required to process the IP core in the Quartus® Prime compiler. Generally, a single .qip file is generated for each IP core.


Includes the HDL files necessary for Quartus® Prime synthesis.


Includes testbench subdirectories for the Aldec, Cadence, Synopsys, and Mentor simulation tools with the required libraries and simulation scripts.


Includes the HDL source files and scripts for the simulation testbench.

For a more detailed listing of the directories and files the Quartus® Prime software generates, refer to Files Generated for Intel IP Cores in Compiling the Design in the Qsys Design Flow.