Stratix V Avalon-ST Interface for PCIe Solutions: User Guide

ID 683093
Date 5/03/2019
Document Table of Contents

5.1. Clock Signals

Table 24.  Clock Signals






Reference clock for the IP core. It must have the frequency specified under the System Settings heading in the parameter editor. This is a dedicated free running input clock to the dedicated REFCLK pin.

If your design meets the following criteria:

  • Enables CvP
  • Includes an additional transceiver PHY connected to the same Transceiver Reconfiguration Controller

then you must connect refclk to the mgmt_clk_clk signal of the Transceiver Reconfiguration Controller and the additional transceiver PHY. In addition, if your design includes more than one Transceiver Reconfiguration Controller on the same side of the FPGA, they all must share the mgmt_clk_clk signal.



Clocks the Application Layer. You can drive this clock with coreclkout_hip. If you drive pld_clk with another clock source, it must be equal to or faster than coreclkout_hip, but cannot be faster than 250 MHz. Choose a clock source with a 0 ppm accuracy if pld_clk is operating at the same frequency as coreclkout_hip.



This is a fixed frequency clock used by the Data Link and Transaction Layers. To meet PCI Express link bandwidth constraints, this clock has minimum frequency requirements as listed in Application Layer Clock Frequency for All Combination of Link Width, Data Rate and Application Layer Interface Width in the Reset and Clocks chapter .