Stratix V Avalon-ST Interface for PCIe Solutions: User Guide

ID 683093
Date 5/03/2019
Document Table of Contents

1.4. Configurations

The Stratix V Hard IP for PCI Express includes a full hard IP implementation of the PCI Express stack including the following layers:

  • Physical (PHY), including:
    • Physical Media Attachment (PMA)
    • Physical Coding Sublayer (PCS)
  • Media Access Control (MAC)
  • Data Link Layer (DL)
  • Transaction Layer (TL)

The Hard IP supports all memory, I/O, configuration, and message transactions. It is optimized for Intel devices. The Application Layer interface is also optimized to achieve maximum effective throughput. You can customize the Hard IP to meet your design requirements.

Figure 2. PCI Express Application with a Single Root Port and EndpointThe following figure shows a PCI Express link between two Stratix V FPGAs.
Figure 3. PCI Express Application Using Configuration via Protocol The Intel® Arria® 10 design below includes the following components:
  • Two Endpoints that connect to a PCIe switch.
  • A host CPU that implements CvP using the PCI Express link connects through the switch.