Intel® Quartus® Prime Timing Analyzer Cookbook

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ID 683081
Date 7/21/2022
Public
Document Table of Contents
Document Table of Contents x
Intel® Quartus® Prime Timing Analyzer Cookbook
Intel® Quartus® Prime Timing Analyzer Cookbook x
Clocks and Generated Clocks I/O Constraints Timing Exceptions Miscellaneous Intel® Quartus® Prime Timing Analyzer Cookbook Document Revision History
Clocks and Generated Clocks x
Basic Non-50/50 Duty Cycle Clock Offset Clocks Offset Clock Constraints Basic Clock Divider Using -divide_by Toggle Register Generated Clock PLL Clocks Multi-Frequency Analysis
Multi-Frequency Analysis x
Clock Multiplexing Externally Switched Clock PLL Clock Switchover
I/O Constraints x
Input and Output Delays with Virtual Clocks Tri-State Outputs System Synchronous Input System Synchronous Output I/O Timing Requirements (tSU, tH, and tCO)
Timing Exceptions x
Multicycle Exceptions False Paths
Miscellaneous x
JTAG Signals Input and Output Delays with Multiple Clocks Clock Enable Multicycle
Intel® Quartus® Prime Timing Analyzer Cookbook

Offset Clocks

When you constrain clocks in the Timing Analyzer, the first rising or falling edge of a clock occurs at an absolute 0 by default. You can create an offset for the clock with the -waveform option.
Figure 2. Simple Register-to-Register Path Clocked by clkB

Offset Clock Constraints

# -waveform defaults to 50/50 duty cycle
create_clock -period 10.000 \
	-name clkA \
	[get_ports {clkA}]
#create a clock with a 2.5 ns offset
create_clock -period 10.000 \
	-waveform {2.500 7.500} \
	-name clkB [get_ports {clkB}]
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