Intel® Quartus® Prime Timing Analyzer Cookbook

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ID 683081
Date 7/21/2022
Public
Document Table of Contents
Document Table of Contents x
Intel® Quartus® Prime Timing Analyzer Cookbook
Intel® Quartus® Prime Timing Analyzer Cookbook x
Clocks and Generated Clocks I/O Constraints Timing Exceptions Miscellaneous Intel® Quartus® Prime Timing Analyzer Cookbook Document Revision History
Clocks and Generated Clocks x
Basic Non-50/50 Duty Cycle Clock Offset Clocks Basic Clock Divider Using -divide_by Toggle Register Generated Clock PLL Clocks Multi-Frequency Analysis
Multi-Frequency Analysis x
Clock Multiplexing Externally Switched Clock PLL Clock Switchover
I/O Constraints x
Input and Output Delays with Virtual Clocks Tri-State Outputs System Synchronous Input System Synchronous Output I/O Timing Requirements (tSU, tH, and tCO)
Timing Exceptions x
Multicycle Exceptions False Paths
Miscellaneous x
JTAG Signals Input and Output Delays with Multiple Clocks Clock Enable Multicycle
Intel® Quartus® Prime Timing Analyzer Cookbook

Multi-Frequency Analysis

Some designs require multiple clocks driving into the FPGA, where one clock might be faster or slower than the other.

Section Content
Clock Multiplexing
Externally Switched Clock
PLL Clock Switchover

Level Two Title