P-Tile Avalon® Streaming Intel® FPGA IP for PCI Express* User Guide

ID 683059
Date 4/10/2023

A newer version of this document is available. Customers should click here to go to the newest version.

Document Table of Contents

G.2. Nx5 Testing Efficiency

The purpose of repeat testing is to quantify Device Under Test (DUT)-to-DUT board copy variation and run-to-run variation. Choosing two or more random boards and sets of silicon can give a good statistical assessment of DUT-to-DUT variation. Performing five power cycled margin runs gives a good average of the boot-to-boot variation to fit to the statistical model. The boot-to-boot variation is why it is important to force the Physical (PHY) Layer to retrain between tests. System INIT cold reboot is used to force the PHY Layer to retrain and is recommended as part of a margining flow as discussed in the following section.

Intel recommends a 5x5 (five test boards with five power cycled margin runs on each) data sample for validating PCIe links. Intel provides a guidance from 2x5 to 5x5 to give you some flexibility in the event that fewer test boards are available.

Contact Intel if there are any questions or concerns with the process or the results.