P-Tile Avalon® Streaming Intel® FPGA IP for PCI Express* User Guide
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Visible to Intel only — GUID: nsv1539647338965
Ixiasoft
Visible to Intel only — GUID: nsv1539647338965
Ixiasoft
2.1.1. Clock Domains
- PHY clock domain (i.e. core_clk domain): this clock is synchronous to the SerDes parallel clock.
- EMIB/FPGA fabric interface clock domain (i.e. pld_clk domain): this clock is derived from the same reference clock (refclk0) as the one used by the SerDes. However, this clock is generated from a stand-alone core PLL.
- Application clock domain (coreclkout_hip): this clock is an output from the P-Tile IP, and it has the same frequency as pld_clk.
The PHY clock domain (i.e. core_clk domain) is a dynamic frequency domain. The PHY clock frequency is dependent on the current link speed.
Link Speed | PHY Clock Frequency | Application Clock Frequency |
---|---|---|
Gen1 | 125 MHz | Gen1 is supported only via link down-training and not natively. Hence, the application clock frequency depends on the configuration you choose in the IP Parameter Editor. For example, if you choose a Gen3 configuration, the application clock frequency is 250 MHz. |
Gen2 | 250 MHz | Gen2 is supported only via link down-training and not natively. Hence, the application clock frequency depends on the configuration you choose in the IP Parameter Editor. For example, if you choose a Gen3 configuration, the application clock frequency is 250 MHz. |
Gen3 | 500 MHz | 250 MHz |
Gen4 | 1000 MHz | 175 MHz / 200 MHz / 225 MHz / 350 MHz / 400 MHz / 450 MHz ( Intel® Stratix® 10 DX) 175 MHz / 200 MHz / 225 MHz / 250 MHz / 350 MHz / 400 MHz / 450 MHz / 500 MHz (Intel Agilex® 7) |