P-Tile Avalon® Streaming Intel® FPGA IP for PCI Express* User Guide
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7.1. Hardware
- Link training
- BIOS enumeration and data transfer
The following sections describe the flow to debug link issues during the hardware bring-up. Intel recommends a systematic approach to diagnosing issues as illustrated in the following figure.
- Protocol and link status information.
- Basic and advanced debugging capabilities including register read access and Eye viewing capability.