The P-Tile Debug Toolkit (DTK) is a System Console-based tool for P-Tile that provides real-time control, monitoring and debugging of the PCIe links at the Physical Layer.
The P-Tile Debug Toolkit allows you to:
- View protocol and link status of the PCIe links.
- View PLL and per-channel status of the PCIe links.
- View the channel analog settings.
- View the receiver eye and measure the eye height and width for each channel.
- Indicate the presence of a re-timer connected between the link partners.
The following figure provides an overview of the P-Tile Debug Toolkit in the P-Tile Avalon® -ST IP for PCI Express.
When you enable the P-Tile Debug Toolkit, the intel_pcie_ptile_ast module of the generated IP includes the Debug Toolkit modules and related logic as shown in the figure above.
Drive the Debug Toolkit from a System Console. The System Console connects to the Debug Toolkit via an Native PHY Debug Master Endpoint (NPDME). Make this connection via an Intel FPGA Download Cable.
A multiplexer is implemented to allow dynamic switching between the user AVMM reconfiguration interface and the System Console-based Debug Toolkit, when the Debug Toolkit is enabled. This allows you to switch between the user logic driving the reconfiguration interface and the Debug Toolkit, as both access the same set of registers within the Hard IP. The user AVMM reconfiguration interface has the default access (the default is when toolkit_mode = 0). Upon launching the Debug Toolkit (DTK) from System Console, toolkit_mode is automatically set to 1 for DTK access. While the DTK is open in System Console, user logic will not be able to drive the signals on the user AVMM interface as the multiplexer is set to toolkit_mode = 1. Upon exiting (closing) the Debug Toolkit window in System Console, toolkit_mode is automatically set to 0 for user access.
The Debug Toolkit can be launched successfully only if pending read/write transactions on the reconfiguration interface are completed (indicated by the deassertion of the reconfig_waitrequest signal).
- The NPDME module
- PHY reconfiguration interface (xcvr_reconfig)
- Hard IP reconfiguration interface (hip_reconfig)
Provide a clock source (50 MHz - 125 MHz, 100 MHz recommended clock frequency) to drive the xcvr_reconfig_clk clock. Use the output of the Reset Release Intel FPGA IP to drive the ninit_done, which provides the reset signal to the NPDME module.
- set_location_assignment PIN_C23 -to xcvr_reconfig_clk_clk
When the Debug Toolkit and the Hard IP Reconfiguration interface are enabled in the dynamically-generated design example, check that the hip_reconfig_clk clock is connected to its respective clock source and the pin assignment is made properly.