P-Tile Avalon® Streaming Intel® FPGA IP for PCI Express* User Guide
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Ixiasoft
F.2.1. P-tile Dual-Endpoint System Configurations
The following table summarizes the dual-endpoint system configurations supported by P-tile:
Configuration Types | REFCLK Source | REFCLK Availability | Port Connectivity | |||
---|---|---|---|---|---|---|
REFCLK0 | REFCLK1 | REFCLK0 | REFCLK1 | Port0 | Port1 | |
A | Free-running 100MHz clock source 1 | Free-running 100MHz clock source 2 | During initial FPGA configuration | During initial FPGA configuration | Local SOC | Host SOC |
B | Free-running 100MHz clock source 1 | Free-running 100MHz clock source 2 | During initial FPGA configuration | During initial FPGA configuration | Host SOC | Local SOC |
C | Free-running 100MHz clock source 1 | Free-running 100MHz clock source 1 | During initial FPGA configuration | During initial FPGA configuration | Local SOC | Host SOC |
D | Free-running 100MHz clock source 1 | PCH | During initial FPGA configuration | May not be active during initial FPGA configuration | Local SOC | Host SOC |
Supported System Configuration Type A: P-tile Port 0 and Port 1 with separate free-running clock sources. Both clocks are available during initial FPGA configuration. Port 0 is connected to a local SOC, Port 1 is connected to the Host.