Intel® High Level Synthesis Accelerator Functional Unit Design Example User Guide

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ID 683025
Date 7/19/2019
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Document Table of Contents
Document Table of Contents x
1. About the HLS AFU Design Example 2. Building the HLS AFU Design Example 3. Customizing the HLS AFU 4. HLS AFU Design Example Description 5. Troubleshooting HLS AFU Designs 6. Document Revision History for the HLS AFU Design Example User Guide
1. About the HLS AFU Design Example x
1.1. HLS AFU Design Example Files 1.2. Acronyms in the HLS AFU Design Example User Guide
2. Building the HLS AFU Design Example x
2.1. HLS AFU Design Example Software Requirements 2.2. Compiling and Simulating the HLS Component with the i++ Command 2.3. Generating a Platform Designer Container for the HLS Component 2.4. Generating the ASE Testbench 2.5. Running the ASE Testbench 2.6. Compiling the AF Bitstream 2.7. Loading AF Bitstream and Running the Host Application
3. Customizing the HLS AFU x
3.1. Acceleration Stack Configuration Files
4. HLS AFU Design Example Description x
4.1. AFU Description 4.2. Host Application Description
4.1. AFU Description x
4.1.1. HLS AFU Container
4.1.1. HLS AFU Container x
4.1.1.1. HLS AFU Avalon-MM I/O Slave Interface 4.1.1.2. HLS AFU Avalon-MM Master Interfaces
5. Troubleshooting HLS AFU Designs x
5.1. Platform Designer Opens with an Error 5.2. The design unit was not found Error When Running the make sim Command 5.3. Verilog HDL Compilation Errors 5.4. Compilation Errors During ASE Testbench Generation 5.5. Incorrect Output During Simulation 5.6. AF Bitstream Compilation Fails 5.7. Verilog Files Not Found Errors
1. About the HLS AFU Design Example
2. Building the HLS AFU Design Example
3. Customizing the HLS AFU
4. HLS AFU Design Example Description
5. Troubleshooting HLS AFU Designs
6. Document Revision History for the HLS AFU Design Example User Guide

2.1. HLS AFU Design Example Software Requirements

Ensure that you configure your system for building Intel Acceleration Stack designs as described in the Intel Acceleration Stack Quick Start Guide for Intel Programmable Acceleration Card with Intel® Arria® 10 GX FPGA

Before you use the design example, install the following software:

  • Intel Acceleration Stack for Development Version 1.2 or later (and associated prerequisites)

    The Acceleration Stack includes Intel® Quartus® Prime Pro Edition Version 17.1.1

  • Intel® High Level Synthesis (HLS) Compiler Version 19.1 or later to compile your HLS code

    Get the Intel® High Level Synthesis Compiler from the Additional Software tab of the Intel® Quartus® Prime Pro Edition Version 19.1 download page at the Download Center for FPGAs.

    For instructions about how to integrate Intel® HLS Compiler Pro Edition Version 19.1 into your Intel® Quartus® Prime Pro Edition Version 17.1.1 installation, review the Intel High Level Synthesis Compiler Getting Started Guide.

  • (Optional) 64-bit Mentor ModelSim* SE* Simulator (Version 10.5c) or 64-bit Mentor Questa* Advanced Simulator (Version 10.5c)

    These simulators are required if you want to simulate the AFU.

    If you want to simulate only the HLS component, you can use the 32-bit ModelSim* - Intel® FPGA Edition software.

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