Intel® High Level Synthesis Accelerator Functional Unit Design Example User Guide

ID 683025
Date 7/19/2019
Public

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5.3. Verilog HDL Compilation Errors

The hls_afu_container Platform Designer system is instantiated in afu.sv. Make sure that the instantiation matches the interface defined in hls_afu/hw/rtl/qsys/hls_afu_container/hls_afu_container_inst.v (which appears after generating the hls_afu_container system in Platform Designer).