Intel® High Level Synthesis Accelerator Functional Unit Design Example User Guide

ID 683025
Date 7/19/2019
Public

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6. Document Revision History for the HLS AFU Design Example User Guide

Document Version Changes
2019.07.19
  • Corrected error in step 6 in Generating a Platform Designer Container for the HLS Component:

    The step now says "After Validate System Integrity successfully completes, click Close.". Previously this step referred to "Sync System Infos".

  • Revised step 10 in Customizing the HLS AFU and added new images to show UI before and after effect of the step.
  • Changed document part number to UG-20246.

    Previously, this document was part number UG-20192.

2019.05.10
  • Updates for Intel® Acceleration Stack for Intel® Xeon® CPU with FPGAs Version 1.2 and Intel® HLS Compiler Pro Edition Version 19.1.
2019.03.12
  • Corrected Correct Directory Structure figure.
2019.01.31
  • Corrected code: $ $OPAE_PLATFORM_ROOT/bin/run.sh
2018.11.30
  • Initial release.