Intel® High Level Synthesis Accelerator Functional Unit Design Example User Guide

ID 683025
Date 7/19/2019

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Document Table of Contents

4.1. AFU Description

Like other AFU designs, the HLS AFU design example defines the top-level functionality of the AFU in The design example implements all the compute functionality of the AFU in the HLS component. However, the design example needs some RTL to initialize and connect the required hardware components.

This design is based on the DMA AFU design, except that this design lacks Avalon-MM master interfaces for communicating with the DRAM banks on the Intel® FPGA PAC.

The most important parts of this design are the CCI-P to Avalon-MM adapter component and MPF BBB. These components buffer CCI-P transactions and translate them to Avalon-MM transactions, and vice-versa.

The MPF BBB and CCI-P to Avalon-MM adapter components included with this design support more of the Avalon specification than the adapter included with the DMA AFU design. For more details about the DMA AFU design, refer to the DMA Accelerator Functional Unit (AFU) User Guide.

These two components connect the HLS component with the Acceleration Stack host, because the Acceleration Stack infrastructure only exposes a CCI-P, not an Avalon-MM interface.

Figure 13. Overview of HLS AFU hardware