DMA Accelerator Functional Unit User Guide: Intel® Programmable Acceleration Card with Intel® Arria® 10 GX FPGA

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ID 683263
Date 3/06/2020
Public
Document Table of Contents
Document Table of Contents
1. About this Document 2. DMA AFU Description 3. Register Map and Address Spaces 4. Software Programming Model 5. Running DMA AFU Example 6. Compiling the Accelerator Function (AF) 7. Simulating the AFU Example 8. DMA Accelerator Functional Unit User Guide Archives 9. Document Revision History for the DMA Accelerator Functional Unit User Guide A. Enabling Hugepages
1. About this Document
1.1. Intended Audience 1.2. Conventions 1.3. Acronyms 1.4. Acceleration Glossary
2. DMA AFU Description
2.1. Introduction 2.2. The DMA AFU Software Package 2.3. The DMA AFU Hardware Components
2.3. The DMA AFU Hardware Components
2.3.1. DMA Test System 2.3.2. DMA BBB
3. Register Map and Address Spaces
3.1. DMA AFU Register Map
3.1. DMA AFU Register Map
3.1.1. DMA AFU Address Space
4. Software Programming Model
4.1. Software APIs
4.1. Software APIs
4.1.1. fpgaDmaOpen() 4.1.2. fpgaDmaTransferSync() 4.1.3. fpgaDmaClose()
5. Running DMA AFU Example
5.1. Optimization for Improved DMA Performance
1. About this Document
2. DMA AFU Description
3. Register Map and Address Spaces
4. Software Programming Model
5. Running DMA AFU Example
6. Compiling the Accelerator Function (AF)
7. Simulating the AFU Example
8. DMA Accelerator Functional Unit User Guide Archives
9. Document Revision History for the DMA Accelerator Functional Unit User Guide
A. Enabling Hugepages

1. About this Document

Updated for:
Intel® Acceleration Stack for Intel® Xeon® CPU with FPGAs 1.2.1
This document describes the OpenCL* implementation for the Intel® Programmable Acceleration Card with Intel® Arria® 10 GX FPGA.
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