DMA Accelerator Functional Unit User Guide: Intel® Programmable Acceleration Card with Intel® Arria® 10 GX FPGA

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ID 683263
Date 3/06/2020
Public
Document Table of Contents
Document Table of Contents x
1. About this Document 2. DMA AFU Description 3. Register Map and Address Spaces 4. Software Programming Model 5. Running DMA AFU Example 6. Compiling the Accelerator Function (AF) 7. Simulating the AFU Example 8. DMA Accelerator Functional Unit User Guide Archives 9. Document Revision History for the DMA Accelerator Functional Unit User Guide A. Enabling Hugepages
1. About this Document x
1.1. Intended Audience 1.2. Conventions 1.3. Acronyms 1.4. Acceleration Glossary
2. DMA AFU Description x
2.1. Introduction 2.2. The DMA AFU Software Package 2.3. The DMA AFU Hardware Components
2.3. The DMA AFU Hardware Components x
2.3.1. DMA Test System 2.3.2. DMA BBB
3. Register Map and Address Spaces x
3.1. DMA AFU Register Map
3.1. DMA AFU Register Map x
3.1.1. DMA AFU Address Space
4. Software Programming Model x
4.1. Software APIs
4.1. Software APIs x
4.1.1. fpgaDmaOpen() 4.1.2. fpgaDmaTransferSync() 4.1.3. fpgaDmaClose()
5. Running DMA AFU Example x
5.1. Optimization for Improved DMA Performance
1. About this Document
2. DMA AFU Description
3. Register Map and Address Spaces
4. Software Programming Model
5. Running DMA AFU Example
6. Compiling the Accelerator Function (AF)
7. Simulating the AFU Example
8. DMA Accelerator Functional Unit User Guide Archives
9. Document Revision History for the DMA Accelerator Functional Unit User Guide
A. Enabling Hugepages

1.3. Acronyms

Table 2.  Acronyms
Acronyms Expansion Description
AF Accelerator Function

Compiled Hardware Accelerator image implemented in FPGA logic that accelerates an application.

AFU Accelerator Functional Unit

Hardware Accelerator implemented in FPGA logic which offloads a computational operation for an application from the CPU to improve performance.

API Application Programming Interface A set of subroutine definitions, protocols, and tools for building software applications.
CCI-P Core Cache Interface

CCI-P is the standard interface AFUs use to communicate with the host.

DFH Device Feature Header Creates a linked list of feature headers to provide an extensible way of adding features.
FIM FPGA Interface Manager

The FPGA hardware containing the FPGA Interface Unit (FIU) and external interfaces for memory, networking, etc.

The Accelerator Function (AF) interfaces with the FIM at run time.

FIU FPGA Interface Unit

FIU is a platform interface layer that acts as a bridge between platform interfaces like PCIe* , UPI and AFU-side interfaces such as CCI-P.

MPF Memory Properties Factory The MPF is a Basic Building Block (BBB) that AFUs can use to provide CCI-P traffic shaping operations for transactions with the FIU.  
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