DMA Accelerator Functional Unit User Guide: Intel® Programmable Acceleration Card with Intel® Arria® 10 GX FPGA

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ID 683263
Date 3/06/2020
Public
Document Table of Contents
Document Table of Contents x
1. About this Document 2. DMA AFU Description 3. Register Map and Address Spaces 4. Software Programming Model 5. Running DMA AFU Example 6. Compiling the Accelerator Function (AF) 7. Simulating the AFU Example 8. DMA Accelerator Functional Unit User Guide Archives 9. Document Revision History for the DMA Accelerator Functional Unit User Guide A. Enabling Hugepages
1. About this Document x
1.1. Intended Audience 1.2. Conventions 1.3. Acronyms 1.4. Acceleration Glossary
2. DMA AFU Description x
2.1. Introduction 2.2. The DMA AFU Software Package 2.3. The DMA AFU Hardware Components
2.3. The DMA AFU Hardware Components x
2.3.1. DMA Test System 2.3.2. DMA BBB
3. Register Map and Address Spaces x
3.1. DMA AFU Register Map
3.1. DMA AFU Register Map x
3.1.1. DMA AFU Address Space
4. Software Programming Model x
4.1. Software APIs
4.1. Software APIs x
4.1.1. fpgaDmaOpen() 4.1.2. fpgaDmaTransferSync() 4.1.3. fpgaDmaClose()
5. Running DMA AFU Example x
5.1. Optimization for Improved DMA Performance
1. About this Document
2. DMA AFU Description
3. Register Map and Address Spaces
4. Software Programming Model
5. Running DMA AFU Example
6. Compiling the Accelerator Function (AF)
7. Simulating the AFU Example
8. DMA Accelerator Functional Unit User Guide Archives
9. Document Revision History for the DMA Accelerator Functional Unit User Guide
A. Enabling Hugepages

9. Document Revision History for the DMA Accelerator Functional Unit User Guide

Document Version Intel® Acceleration Stack Version Changes
2020.03.06 1.2.1 (supported with Intel® Quartus® Prime Pro Edition Edition 19.2)
  • Added following new sections:
    • Compiling the Accelerator Function (AF)
    • Simulating the AFU Example
    • Enabling Hugepages
  • Modified the path of the Platform Designer system that implements the DMA AFU and the DMA BBB block in section The DMA AFU Hardware Components.
  • Modified steps to run the DMA AFU in section Running DMA AFU Example.
2018.12.04 1.2 (supported with Intel® Quartus® Prime Pro Edition 17.1.1)
  • Added new section Optimization for Improved DMA Performance.
  • Added new path for a Platform Designer system in The DMA AFU Hardware Components section.
  • Modified command in Running DMA AFU Example section.
2018.08.15 1.1 (supported with Intel® Quartus® Prime Pro Edition 17.1.1) and 1.0 (supported with Intel® Quartus® Prime Pro Edition 17.0.0)
  • Corrected the broken link in DMA Test System.
  • Minor edits in Running DMA AFU Example.
2018.08.06 1.1 (supported with Intel® Quartus® Prime Pro Edition 17.1.1) and 1.0 (supported with Intel® Quartus® Prime Pro Edition 17.0.0)
  • Modified DMA AFU Block Diagram to show that MMIO Decoder Logic is used in place of Asynchronous Shim BBB for CCI-P transactions.
  • Modified the environment variable from $DCP_LOC to $OPAE_PLATFORM_ROOT in the Running DMA AFU Example section.
2018.04.11 1.0 (supported with Intel® Quartus® Prime Pro Edition 17.0.0)
  • Updated Figure: DMA AFU Hardware Block Diagram to include the DMA BBB.
  • Updated information in
    • The DMA AFU Hardware Components
    • Register Map and Address Spaces
    • Running DMA AFU Example
  • Corrected the title of the reference document from the Altera Acceleration Stack for Intel Xeon CPU with FPGAs Getting Started Guide to Intel Acceleration Stack Quick Start Guide for Intel Programmable Acceleration Card with Intel Arria 10 GX FPGA in The DMA AFU Software Package section.
  • Editorial modifications.
2017.12.22 1.0 Beta (supported with Intel® Quartus® Prime Pro Edition 17.0.0) Initial release.
Level Two Title