DMA Accelerator Functional Unit User Guide: Intel® Programmable Acceleration Card with Intel® Arria® 10 GX FPGA

ID 683263
Date 3/06/2020
Public

2.3.1. DMA Test System

The DMA test system tests the DMA AFU.
Figure 2. DMA Test System Block DiagramThis block diagram shows the internals of the DMA test system. The DMA test system is shown as a monolithic block in .

The DMA test system includes the following internal modules:

  • AFU ID: This component stores the 64-bit Device Feature Header (DFH) and also includes the universally unique identifier (UUID). The AFU_ID_L register stores the lower 32 bits of the AFU ID. The AFU_ID_H register stores the upper 32 bits of the AFU ID. A software driver scans the DMA Test System, finds the AFU ID, and identifies the DMA BBB.
  • DMA Basic Building Block (BBB): This component moves data between the host and local device memory spaces. DMA BBB interrupt connects to the IRQ 0 signal. The IRQ 0 signal is an input to the CCI-P to Avalon® Adapter. The CCI-P to Avalon® Adapter forwards the interrupt to the host.
  • Pipeline Bridge: The Pipeline Bridge inserts pipeline stages between memory mapped IP cores. By default, Platform Designer optimizes for low latency. Consequently, the Pipeline Bridge improve the system maximum operating frequency (FMAX ) at the expense of additional latency.
  • Clock Crossing Bridge: The Clock Crossing Bridge isolates Avalon® -MM masters and slaves that are in different clock domains. Because the Clock Crossing Bridge includes clock-crossing logic, it adds FIFOs that have a greater latency than the standard Pipeline Bridge. The Clock Crossing Bridge ensures that the memory transactions from the DMA BBB safely cross to the local SDRAM clock domain.

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