Intel® High Level Synthesis Accelerator Functional Unit Design Example User Guide

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ID 683025
Date 7/19/2019
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Document Table of Contents
Document Table of Contents x
1. About the HLS AFU Design Example 2. Building the HLS AFU Design Example 3. Customizing the HLS AFU 4. HLS AFU Design Example Description 5. Troubleshooting HLS AFU Designs 6. Document Revision History for the HLS AFU Design Example User Guide
1. About the HLS AFU Design Example x
1.1. HLS AFU Design Example Files 1.2. Acronyms in the HLS AFU Design Example User Guide
2. Building the HLS AFU Design Example x
2.1. HLS AFU Design Example Software Requirements 2.2. Compiling and Simulating the HLS Component with the i++ Command 2.3. Generating a Platform Designer Container for the HLS Component 2.4. Generating the ASE Testbench 2.5. Running the ASE Testbench 2.6. Compiling the AF Bitstream 2.7. Loading AF Bitstream and Running the Host Application
3. Customizing the HLS AFU x
3.1. Acceleration Stack Configuration Files
4. HLS AFU Design Example Description x
4.1. AFU Description 4.2. Host Application Description
4.1. AFU Description x
4.1.1. HLS AFU Container
4.1.1. HLS AFU Container x
4.1.1.1. HLS AFU Avalon-MM I/O Slave Interface 4.1.1.2. HLS AFU Avalon-MM Master Interfaces
5. Troubleshooting HLS AFU Designs x
5.1. Platform Designer Opens with an Error 5.2. The design unit was not found Error When Running the make sim Command 5.3. Verilog HDL Compilation Errors 5.4. Compilation Errors During ASE Testbench Generation 5.5. Incorrect Output During Simulation 5.6. AF Bitstream Compilation Fails 5.7. Verilog Files Not Found Errors
1. About the HLS AFU Design Example
2. Building the HLS AFU Design Example
3. Customizing the HLS AFU
4. HLS AFU Design Example Description
5. Troubleshooting HLS AFU Designs
6. Document Revision History for the HLS AFU Design Example User Guide

2.2. Compiling and Simulating the HLS Component with the i++ Command

As with other HLS design examples, you can compile this example design using the included makefile. This makefile uses similar conventions to the HLS design examples.
Ensure your development environment includes the Intel® HLS Compiler Pro Edition Version 19.1 or later.
Note: The HLS code might not compile if you are using the Intel® HLS Compiler Pro Edition Version 19.1 in an environment that does not have the correct version of the GCC libraries. To ensure that you have the correct libraries, review the instructions in the Intel High Level Synthesis Compiler Getting Started Guide.
  1. Initialize your current session so that you can run the Intel® HLS Compiler. In your terminal session, change directories to the hls directory in your Acceleration Stack installation directory.
    For example: 
    $ cd /home/<username>/inteldevstack/intelFPGA_pro/hls
  2. Run the following command from the hls directory to set the environment variables for the i++ command in the current terminal session: 
    $ source init_hls.sh
    The environment initialization script shows the environment variables that it sets.
  3. Navigate to the HLS soruce code.
    The HLS source code is in <design location>/hls_afu/hw/rtl/hls/.
  4. Build and emulate the design using x86 instructions run these commands: 
    $ make test-x86-64
$ ./test-x86-64
    The test-x86-64 command gives you the following output: 
    i++ src/hls_afu.cpp src/test.cpp   --fp-relaxed -ghdl  -march=x86-64 -o test-x86-64
+--------------------------------------------+
| Run ./test-x86-64 <n> to execute the test. |
| <n> is 0, 1, or 2 depending on desired     |
| test behavior:                             |
|         <n> | effect                       |
|       ------+--------------------          |
|          0  | test both (default)          |
|          1  | test ac_int only             |
|          2  | test float only              |
+--------------------------------------------+
Control which component gets tested by passing an integer!
arg   | effect
------+--------------------
   0  | test both (default)
   1  | test ac_int only
   2  | test float only
test AC_INT version and FLOAT version

AC_INT COMPONENT - 81 ELEMENTS
ac_inc:
sizeof(uint512) = 64 (64)
number of 512 bit (64-byte) numbers: 6
PASS

FLOATING-POINT COMPONENT - 81 ELEMENTS
fp_inc:
PASS
OVERALL:
PASSED
  5. Generate RTL and simulate generated RTL with the ModelSim simulator: 
    $ make test-fpga
$ ./test-fpga
    The test-fpga command gives you the following output: 
    Control which component gets tested by passing an integer!
arg   | effect              
------+-------------------- 
   0  | test both (default) 
   1  | test ac_int only    
   2  | test float only     
test AC_INT version and FLOAT version

AC_INT COMPONENT - 81 ELEMENTS
ac_inc:
sizeof(uint512) = 64 (64)
number of 512 bit (64-byte) numbers: 6
PASS

FLOATING-POINT COMPONENT - 81 ELEMENTS
fp_inc:
PASS
OVERALL:
PASSED
  6. Confirm that the outputs from the test-x86-64 command and the test-fpga command match.

    The test-x86-64 command runs C++ code on the processor, while the test-fpga command compiles the C++ source to to Verilog RTL and then simulates the generate RTL using the testbench defined in the code.

    For instructions about how to view the waveforms for this component, see the Intel High Level Synthesis Compiler User Guide.

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